Skip to main content

Hello World


A Hello Word program in system verilog

Code

// A Hello Word Program in SV
module test;    
  initial begin
    $display("\nHello Word!!");
  end
endmodule

Popular posts from this blog

UVM Introduction

UVM Intro Universal Verification Methodology (UVM)  is a standard to enable faster development and reuse of verification environments and VIP's. The UVM Class Library provides generic utilities, such as component hierarchy, transaction library model (TLM), configuration database, etc., which enable the user to create virtually any structure of choice.